题目：Transactional Server Processors � A Bright Future Ahead
报告人：Nhon Quach教授
时间：2005年9月13日下午2:30
地点：曹光彪东楼502会议室
附：Nhon Quach教授简历
Nhon Quach has over 15 years of industry experience in microprocessor design at various companies including AMD, Oracle, Intel and IBM. He is currently a processor architect at AMD working on the definition of a next generation server processor. At Oracle, he set hardware and software optimization strategies for various server platforms in the virtual OS server technology group. Prior to joining Oracle, he was the system architect as well as the manager of the Itanium system architecture group at Intel and defined the RAS architecture for the first generation Itanium processor. As an intern at IBM, he wrote a prototype compiler demonstrating a novel vectorization-based code scheduling technique for the Intel i860 processor. He is a widely recognized expert in the areas of floating-point (FP) hardware design and system RAS. His publication on the Itanium processor RAS features is often a required reading in many computer architecture courses in the U.S. As a consultant, he was the architect and manager of the FP units used in the SGI Indigo II workstation graphics subsystem. His Ph.D. research work at Stanford on high-speed integer addition, integrated rounding for FP addition, and systematic rounding for FP multiplication has been widely adopted in the FP hardware design community today.
Nhon Quach received the Ph.D. degree in computer architecture from Stanford University in 1994, the Masters degree from MIT in 1984, and the B.S. degree from the University of Texas at Austin in 1982. His technical interests include computer system architecture and design in the area of SOC (system on chip), parallel processing, fault-tolerant computing, advanced processor implementation techniques, and advanced computer arithmetic especially in the areas of compression and encryption. He is currently an adjunct professor at San Jose State University, teaching advanced courses in computer architecture and multiprocessor system implementation and design.
Dr. Quach has over 20 publications and holds 20 issued U.S. patents in system reliability and processor design.
计算机学院(软件学院)
2005年9月8日
报告人：Nhon Quach教授
时间：2005年9月13日下午2:30
地点：曹光彪东楼502会议室
附：Nhon Quach教授简历
Nhon Quach has over 15 years of industry experience in microprocessor design at various companies including AMD, Oracle, Intel and IBM. He is currently a processor architect at AMD working on the definition of a next generation server processor. At Oracle, he set hardware and software optimization strategies for various server platforms in the virtual OS server technology group. Prior to joining Oracle, he was the system architect as well as the manager of the Itanium system architecture group at Intel and defined the RAS architecture for the first generation Itanium processor. As an intern at IBM, he wrote a prototype compiler demonstrating a novel vectorization-based code scheduling technique for the Intel i860 processor. He is a widely recognized expert in the areas of floating-point (FP) hardware design and system RAS. His publication on the Itanium processor RAS features is often a required reading in many computer architecture courses in the U.S. As a consultant, he was the architect and manager of the FP units used in the SGI Indigo II workstation graphics subsystem. His Ph.D. research work at Stanford on high-speed integer addition, integrated rounding for FP addition, and systematic rounding for FP multiplication has been widely adopted in the FP hardware design community today.
Nhon Quach received the Ph.D. degree in computer architecture from Stanford University in 1994, the Masters degree from MIT in 1984, and the B.S. degree from the University of Texas at Austin in 1982. His technical interests include computer system architecture and design in the area of SOC (system on chip), parallel processing, fault-tolerant computing, advanced processor implementation techniques, and advanced computer arithmetic especially in the areas of compression and encryption. He is currently an adjunct professor at San Jose State University, teaching advanced courses in computer architecture and multiprocessor system implementation and design.
Dr. Quach has over 20 publications and holds 20 issued U.S. patents in system reliability and processor design.
计算机学院(软件学院)
2005年9月8日
